1. Field of the Invention
The present invention relates to a technique for designing a large-scale hardware macro for an ASIC (Application Specific Integrated Circuit), and more particularly it relates to an ASIC design method and ASIC designing apparatus which eliminate redundant interconnections and increases the interconnect region usable for user logic when a large-scale macro is implemented on an ASIC.
2. Background of the Invention
FIG. 8 shows a flow chart that illustrates a method of designing an ASIC according to the prior art. In the ASIC design method of the prior art shown in FIG. 8, a primitive library, micro library, and net list are used to perform layout and wiring, without eliminating redundant circuits from the macro, after which a delay simulation is performed. In the past, to implement a circuit having a large-scale hardware macro made up of primitive macros, either layout and wiring were made without eliminating redundant circuits, or a macro of the desired specifications was designed anew. Because the specifications of the actual macro differ from customer to customer, the result is that general-purpose macros include different redundant portions for individual customers. To optimize this, a macro is developed anew for the customer specifications, in which case the term required to develop a new macro is approximately 3 months, thereby greatly increasing the time and cost required for development. In the case in which an existing macro is used as is, because interconnection data including redundant circuits have priority for customers, there is a worsening of the interconnections in the customer""s designed circuit. For example, in the case in which only a DMA controller with a 16-it data bus is available in the macro library, a macro having a 16-it data bus will be used, even though only an 8-bit data bus is used, the remaining buses that are not needed in the chip become redundant circuits. The result of this is a worsening of interconnections of the user logic. In the Japanese Patent 2,752,923, for example, there is a description for eliminating such redundancies. Specifically, according to the prior art of Japanese Patent 2,752,923 as shown in FIG. 9, in a logic simulation apparatus having a redundant circuits removal means 23 which, based on first logic descriptive information 21 and operation mode control information 22 for the circuit to be designed, generates third logical descriptive information 38 by performing logic simulation and removing from the first logic descriptive information 21 redundant circuits that are not needed in the circuit to be designed, a logic synthesis means 24 for performing logic synthesis based on the third logic descriptive information 38 so as to generate a gate-level output logic circuit 25, and a second logic simulation means 26 for evaluating the output logic circuit 25, the redundant circuits removal means 23 of this logic simulation apparatus further has a conditional statement searching means 31 for searching for a conditional statement indicating an input-to-output condition from among the first logic descriptive information 21, a state transition display description appending means 32 which, based on the retrieved conditional statement, generates second logic descriptive information 33 with state transition information added by the means 32, a first logic simulation means 34 which receives the operating mode control information 22 and the second logic descriptive information 33, performs a logic simulation, and outputs state value information 35, which is the result of the simulation, a fixed conditional statement judgment means 36 which, based on state value information 35, judges and extracts a fixed conditional statement corresponding to a redundant circuits, and a fixed conditional statement removal means 37 which, based on the results of the judgment, removes a fixed conditional statement from the first logic descriptive information 21, so as to generate a third logic description file 38. By this configuration, a condition statement is searched in the input macro logic description file 21 and, by means of the results of simulation of logic description file to which a state transition display statement has been added, it is possible to make a judgment on a fixed condition and to remove this fixed condition from the original logic code so as to remove a redundant portions from the circuit, thereby enabling automatic removal of redundant portions from the circuit, shortening the design turnaround time, and also reducing the number of elements in the integrated circuit, which reduces the area of the circuit, the result of which is a reduction in cost.
In the prior art, however, while there is a large degree of freedom in removal at the function description level, it is necessary to perform evaluation of layout, wiring and delay times many times, this being a problem in the design of an ASIC for a particular customer.
Accordingly, in consideration of the above-noted drawback of the prior art, it is an object of the present invention to provide an ASIC design method and ASIC design apparatus which removes redundant interconnections when implementing a large-scale hardware macro in an ASIC, and which increase the interconnect region usable by user logic.
In order to achieve the above-noted objects, the first aspect of the present invention has the following basic technical constitution.
Specifically, a first aspect of the present invention is a method for designing an ASIC having a first step of generating circuit data that includes a large-scale hardware macro made up of primitive macros; a second step of extracting, from the circuit data generated in the first step, wiring data of an external terminal of the large-scale hardware macro, an output of which is in an open state or an input of which is clamped; a third step of performing circuit tracing using the wiring data of the external terminal extracted in the second step; a fourth step of removing wiring data of a redundant primitive macro and redundant wiring data connected to said redundant primitive macros using the wiring data of the external terminal extracted in the second step; a fifth step of generating a temporary library in which a delay time within the macro is adjusted, based on removal results obtained in the fourth step; and a sixth step of performing layout and wiring, and of performing a delay simulation, using the temporary library generated in the fifth step.
In a second aspect of the present invention, the fourth step includes a step of prohibiting a removal of wiring data of a clock line in a flip-flop circuit.
In a third aspect of the present invention, the fourth step includes a step of prohibiting a removal of wiring data having a branch circuit in a net list, when the wiring data of the external terminal extracted in the second step includes a branch circuit.
In a fourth aspect of the present invention, the fourth step includes a step of setting removal prohibition information within the library, so as to impart a limitation on the removal of wiring data of redundant primitive macros and redundant wiring data connected to the redundant primitive macros.
A fifth aspect of the present invention is an apparatus for designing an ASIC comprising a first means of generating circuit data that includes a large-scale hardware macro made up of primitive macros; a second means of extracting, from the circuit data generated in the first means, wiring data of an external terminal of the large-scale hardware macro, an output of which is in an open state or an input of which is clamped; a third means of performing circuit tracing using the wiring data of the external terminal extracted in the second means; a fourth means of removing wiring data of a redundant primitive macro and redundant wiring data connected to said redundant primitive macros using the wiring data of the external terminal extracted in the second means; a fifth means of generating a temporary library in which a delay time within said macro is adjusted, based on an output of said fourth means; and a sixth means of performing layout and wiring, and of performing a delay simulation, using the temporary library generated in the fifth means.
In a sixth aspect of the present invention, the fourth means includes a means of prohibiting a removal of wiring data of a clock line in a flip-flop circuit.
In a seventh aspect of the present invention, the fourth means includes a means of prohibiting a removal of wiring data having a branch circuit in a net list, when the wiring data of the external terminal extracted in the second means includes a branch circuit.
In an eighth aspect of the present invention, the fourth means includes a means of setting removal prohibition information within the library, so as to impart a limitation on the removal of wiring data of a redundant primitive macro and redundant wiring data connected to the redundant primitive macros.